Generally, for an operational amplifier circuit implemented in a given technology, the product of the amplifier's gain and maximum bandwidth is constant. Consequently, the design of an operational amplifier circuit typically involves compromising between high gain and high bandwidth. Thus, a designer must decide which parameter is more important for a particular application and design the operational amplifier circuit accordingly (i.e., the designer "trades off" gain for bandwidth, or vice versa).
Further, the slew rate (i.e., the rate at which the output voltage changes) of an operational amplifier circuit, in general, increases as bandwidth increases. Because an amplifier's slew rate increases with the amplifier's bandwidth, the designer also trades off gain for slew rate (or vice versa).
FIG. 1 (Prior Art) shows a schematic diagram of a typical unity gain buffer circuit. Buffer circuit 100 includes operational amplifier 101 and drives a load 120. Load 120 is both resistive and capacitive, and represents the loading "seen" by buffer circuit 100 when driving the input of another circuit.
The output of buffer circuit 100 is determined by the equation: EQU Vout=Vin/(1+1/A)
where A is the open loop gain of amplifier 101. For a unity gain buffer circuit, gain A must be sufficiently high so that voltage Vout is substantially equal to voltage Vin. However, as described above, the designer must trade off slew rate for gain. Thus, if the designer chooses to design buffer circuit with a high gain amplifier to more closely achieve unity gain, the buffer circuit's slew rate is decreased. A low slew rate may introduce error into the buffer circuit's output signal (described below in conjunction with FIG. 2). Thus, in applications requiring both unity gain and high slew rate from the same buffer, buffer circuit 100 is inadequate. One such application is an integrator circuit (discussed below in conjunction with FIG. 4).
FIG. 2 shows the output waveform of the buffer circuit 100 (FIG. 1) to a step input signal. Buffer circuit 100, in response to a step input signal having a voltage of v.sub.1 represented by Vin waveform 200, generates at LOADOUT node 110 (FIG. 1) an output signal represented by LOADOUT waveform 210. Ideally, LOADOUT waveform 210 is identical to Vin waveform 200. However, because buffer circuit 100 has a finite slew rate and because of the loading due to load 120, buffer circuit 100 requires time t1 to drive the voltage at LOADOUT node 110 from ground potential to voltage v.sub.1. Similarly, buffer circuit 100 requires time t2 to drive LOADOUT node 110 from voltage v.sub.1 to ground potential. Shaded areas A1 and A2 represent deviation by buffer circuit 100 from the ideal performance. Thus, as the slew rate of buffer circuit 100 decreases, areas A1 and A2 increase.
For some applications (such as an integrator circuit, which measures the total area under waveform 210) area A1 lost during the ramp up is offset by area A2 gained during the ramp down. However in general the positive going slew rate is different from the negative going slew rate and thus A1 and A2 have an area mismatch. In practice, it is very difficult to match the positive and negative going slew rates.